A virtual ground memory array architecture is often used for flash memory arrays, such as floating gate flash memory arrays. During a typical conventional fabrication process for a virtual ground floating gate memory array, a layer of silicon nitride can be deposited, patterned, and etched to form silicon nitride segments on a layer of silicon oxide, which is formed on a substrate. A dopant, such as arsenic, can then be implanted in the substrate in gaps between adjacent silicon nitride segments to form bitlines. An oxidation process is next performed to grow a thick oxide layer over each bitline, and the silicon nitride segments are removed. A tunnel oxide layer is then formed over the substrate, and a layer of polysilicon is deposited, patterned, and etched to form polysilicon segments over the tunnel oxide layer.
However, in the conventional fabrication process discussed above, the oxidation process that is performed after the bitline implant requires a high thermal cycle, which can cause undesirable bitline dopant diffusion. Another problem with the conventional fabrication process discussed above is that the bitline implant is not self-aligned to the polysilicon segments, which can undesirably affect virtual ground floating gate memory array reliability.
Virtual ground memory arrays, such as virtual ground flash memory arrays, have also been formed using an Oxide-Nitride-Oxide (ONO) stack for localized charge storage. However, virtual ground memory arrays formed using an ONO stack for charge storage can be difficult to scale and can have low reliability.
Thus, there is a need in the art for an effective method for fabricating a virtual ground memory array, such as a virtual ground flash memory array, having increased reliability and scalability.